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| CY25822-2 CK-SSC Spread Spectrum Clock Generator Features 3.3V operation 48- and 66-MHz frequency support Selectable slew rate control 350-pS jitter I2C programmability 500-A power-down current Spread Spectrum for best electromagnetic interference (EMI) reduction * 8-pin SOIC package * * * * * * * Block Diagram VDD REFOUT CLKOUT (SSCG Output) Clock Input Freq. Divider M Phase Detector Charge Pump VCO Post Dividers SDATA SCLOCK PWRDWN# Logic Control Feedback Divider N Modulating Waveform PLL GND Pin Configuration C L K IN 1 VDD 2 8 *P W R D W N # 7 SC LO C K C Y 2 5 8 2 2 -2 GND 3 C LKO U T 4 * 1 5 0 K P u ll-u p 6 SDATA 5 REFOUT Cypress Semiconductor Corporation Document #: 38-07531 Rev. ** * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised March 18, 2003 CY25822-2 Pin Description Pin No. 1 2 3 4 5 6 7 8 Pin Name CLKIN VDD GND CLKOUT REFOUT SDATA SCLOCK PWRDWN# Pin Type Input Power Ground Output Output I/O Input Output Pin Description 48-MHz or 66-MHz Clock Input. Power Supply for PLL and Outputs. Ground for Outputs. 48-MHz or 66-MHz Spread Spectrum Clock Output. Non-spread Spectrum Reference Clock Output. I2C-compatible SDATA. I2C-compatible SCLOCK. LVTTL Input for PowerDown# Active Low. Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions such as individual clock output buffers, etc., can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Table 1. Command Code Definition Bit 7 0 = Block read or block write operation 1 = Byte read or byte write operation Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operation from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individual indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 1. The block write and block read protocol is outlined in Table 2 while Table 3 outlines the corresponding byte write and byte read protocol.The slave receiver address is 11010100 (D4h). Description (6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 .... .... .... Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '00000000' stands for block operation Acknowledge from slave Byte Count - 8 bits Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data byte 2 - 8 bits Acknowledge from slave ...................... Data Byte (N-1) -8 bits Acknowledge from slave Description Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '00000000' stands for block operation Acknowledge from slave Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Byte count from slave - 8 bits Acknowledge Data byte from slave - 8 bits Acknowledge Data byte from slave - 8 bits Page 2 of 9 Block Read Protocol Description Document #: 38-07531 Rev. ** CY25822-2 Table 2. Block Read and Block Write Protocol (continued) .... .... .... Data Byte N -8 bits Acknowledge from slave Stop 56 .... .... .... .... Table 3. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '1xxxxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte from master - 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '1xxxxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Data byte from slave - 8 bits Not Acknowledge Stop Byte Read Protocol Description Acknowledge Data bytes from slave/Acknowledge Data byte N from slave - 8 bits Not Acknowledge Stop 19 20:27 28 29 19 20 21:27 28 29 30:37 38 39 Byte 0: Control Register Bit 7 6 5 4 3 2 @Pup 1 0 0 0 1 1 4, 5 Pin# 4 4 4 4 SS0 SS1 SS2 SS3 Not Applicable CLKOUT, REFOUT CLKOUT Not Applicable Name - - - - Reserved, must be written as 1 Power-down three-state enable 0 = three-state outputs, 1 = drive outputs low (Applies only in Power Down State) Spread Spectrum enable 0 = spread off, 1 = spread on No Pins Pin Description 1 0 1 0 4 Table 4. Spread Spectrum Select SS3 0 0 0 0 0 SS2 0 0 0 0 1 SS1 0 0 1 1 0 SS0 0 1 0 1 0 Spread Mode Down Down Down Down Down Spread Amount% 0.8 1.0 1.25 1.5 1.75 Page 3 of 9 Document #: 38-07531 Rev. ** CY25822-2 Table 4. Spread Spectrum Select (continued) SS3 0 0 0 1 1 1 1 1 1 1 1 SS2 1 1 1 0 0 0 0 1 1 1 1 SS1 0 1 1 0 0 1 1 0 0 1 1 SS0 1 0 1 0 1 0 1 0 1 0 1 Spread Mode Down Down Down Center Center Center Center Center Center Center Center Spread Amount% 2.0 2.5 3.0 0.3 0.4 0.5 0.6 0.8 1.0 1.25 1.5 Byte 1: Control Register Bit 7 6 5 4 3 2 1 0 @Pup 1 1 0 0 1 1 0 0 4 4 Pin# 5 5 REFEN REFSLEW Not Applicable Not Applicable CLKSLEW CLKEN Not Applicable Not Applicable Name Pin Description REFOUT enable 0 = disabled, 1 = enabled REFOUT edge rate control 0 = slow, 1 = nominal Reserved. Reserved CLKOUT edge rate control 0 = slow, 1 = nominal CLKOUT enable 0 =disabled, 1 = enabled Reserved Reserved Bytes 2 through 5: Reserved Registers Byte 6: Vendor/Revision ID Register Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 1 0 0 0 Pin# - - - - - - - - Name - - - - - - - - Pin Description Revision ID Bit 3 Revision ID Bit 2 Revision ID Bit 1 Revision ID Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 PWRDWN# (Power-down) Clarification The PWRDWN# (Power-down) pin is used to shut off ALL clocks prior to shutting off power to the device. PWRDWN# is an asynchronous active LOW input. This signal is synchronized internally to the device powering down the clock synthesizer. PWRDWN# is an asynchronous function for powering up the system. When PWRDWN# is low, all clocks are driven to a LOW value and held there and the VCO and PLLs are also powered down. All clocks are shut down in a synchronous manner so has not to cause glitches while transitioning to the low `stopped' state. When PWRDWN# is deasserted the clocks should remain stopped until the VCO is stable and within specification (tSTABLE). A stopped clock is either tri-stated or driven low depending on the state of the tri-state enable I2C register bit. CY25822 clocks that are stopped in the driven state are driven low. The CLKIN input must be on and within specified operating parameters before PWRDWN# is asserted and it must remain in this state while PWRDWN# is asserted. Document #: 38-07531 Rev. ** Page 4 of 9 CY25822-2 PWRDWN# CLKOUT REFOUT Figure 1. Power-down Assertion PD# C LK O U T R E FO U T <3.0m s Figure 2. Power-down Deassertion CLKOUT and REFOUT Enable Clarification The CLKOUT enable and REFOUT enable I2C register bits are used to shot-off the CLKOUT and REFOUT clocks individually. The VCO and crystal oscillator must remain on. A shutdown clock is driven low. ALL clocks need to be stopped in a predictable manner. All clocks need to be shutdown without any glitches or other abnormal behavior while transitioning to a stopped state. Similarly when CLKOUT or REFOUT is enabled the clock must start in a predictable manner without any glitches or abnormal behavior. Document #: 38-07531 Rev. ** Page 5 of 9 CY25822-2 Table 5. Absolute Maximum Ratings Parameter VDD VDD_A VIN TS TA TJ ESDHBM UL-94 MSL Description Core Supply Voltage Analog Supply Voltage Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction ESD Protection (Human Body Model) Flammability Rating Moisture Sensitivity Level Relative to V SS Non Functional Functional Functional MIL-STD-883, Method 3015 @1/8 in. Condition Min. -0.5 -0.5 -0.5 -65 0 - 2000 V-0 1 Max. 4.6 4.6 VDD + 0.5 +150 70 150 - Unit V V VDC C C C Volts Table 6. DC Parameters (TA = 0C to +70C, VDD = 3.3V 5%) Parameter VDD VIH VIL IIL1 IIL2 VOH Description Supply Voltage Input High Voltage Input Low Voltage Input Leakage Current Input Leakage Current Output High Voltage Condition - - - SCLOCK or SDATA PWRDWN# IOH = -4 mA Min. 3.135 2.0 VSS - 0.3 -25 -75 2.4 Max 3.465 VDD + 0.3 0.8 +25 -15 - Unit V V V A A V Single edge is required to be monotonic when transitioning through this region. Single edge is required to be monotonic when transitioning through this region. Notes VDD = 3.3 5% VOL Output Low Voltage IOL = 4 mA - 0.4 V CIN COUT LIN TA IDD1 IDD2 IPD Input Pin Capacitance Output Pin Capacitance Pin Inductance Ambient Temperature Supply Current Supply Current Power Down Supply Current - - - - @ 66 MHz @ 48 MHz - - - - 0 - - - 5 6 7 70 50 40 500 pF pF nH C mA mA A No air flow Table 7. AC Parameters (TA = 0C to +70C, VDD = 3.3V 5%) Parameter tHIGH tLOW tHIGH tLOW tRISEH1 tFALLH1 tRISEL1 Description CLK High Time, 48MHz CLK, Low Time, 48MHz CLK High Time, 66MHz CLK Low Time, 66MHz Rising Edge Rate Falling Edge Rate Rising Edge Rate Conditions Measured @2.4V Measured @0.4V Measured @2.4V Measured @0.4V Measured from 0.4V to 2.4V REFOUT and CLOCKOUT Measured from 2.4V to 0.4V REFOUT and CLOCKOUT Measured from 0.4V to 2.4V REFOUT and CLOCKOUT Min. 9.45 8.50 6.85 5.95 2.0 2.0 1.33 Max. 10.95 10.10 7.90 6.95 5.0 5.0 4.0 Unit ns ns ns ns Notes Specification applies to 48MHz output mode. Specification applies to 48MHz output mode. Specification applies to 66.7MHz output mode. Specification applies to 66.7MHz output mode. V/ns High Buffer Strength Refer to I2C Control V/ns High Buffer Strength Refer to I2C Control V/ns Low Buffer Strength Refer to I2C Control Document #: 38-07531 Rev. ** Page 6 of 9 CY25822-2 Table 7. AC Parameters (TA = 0C to +70C, VDD = 3.3V 5%) (continued) Parameter tFALLL1 tRISEH2 tFALLH2 tRISEL2 tFALLL2 TCYC1 TCYC2 LTJ Description Falling Edge Rate Rise Time Fall Time Rise Time Fall Time Cycle to Cycle Jitter Cycle to Cycle Jitter Conditions Measured from 2.4V to 0.4V REFOUT and CLOCKOUT Measured from 0.4V to 2.4V REFOUT and CLOCKOUT Measured from 2.4V to 0.4V REFOUT and CLOCKOUT Measured from 0.4V to 2.4V REFOUT and CLOCKOUT Measured from 2.4V to 0.4V REFOUT and CLOCKOUT REFOUT CLOCKOUT Min. 1.33 0.4 0.4 0.5 0.5 - - - Max. 4.0 1.0 1.0 1.5 1.5 500 250 2.0 Unit Notes V/ns Low Buffer Strength Refer to I2C Control ns ns ns ns ps ps ns High Buffer Strength Refer to I2C Control High Buffer Strength Refer to I2C Control Low Buffer Strength Refer to I2C Control Low Buffer Strength Refer to I2C Control SSCG is ON SSCG is ON - 10S Period Jitter Applies to REFOUT at all (100KHz, Frequency Mod- times and CLOCKOUT when ulation Amplitude) SSCG is Off Start up time From VDD = 2.0 V tSTART - 3.0 ms All outputs disabled Table 8. Signal Loading Table Clock Name CLKOUT, REFOUT Max Load (pF) 15 Ordering Information Part Number CY25822SC-2 CY25822SC-2T 8-pin SOIC 8-pin SOIC - Tape and Reel Package Type Product Flow Commercial, 0C to 70C Commercial, 0C to 70C Document #: 38-07531 Rev. ** Page 7 of 9 CY25822-2 Package Diagram 8-lead (150-Mil) SOIC - S8 51-85066-*B Purchase of I2C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.All product and company names mentioned in this document are trademarks of their respective holders. Document #: 38-07531 Rev. ** Page 8 of 9 (c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY25822-2 Document History Page Document Title: CY25822-2 CK-SSC Spread Spectrum Clock Generator Document Number: 38-07531 REV. ** ECN NO. 124462 Issue Date 03/19/03 Orig. of Change RGL New Data Sheet Description of Change Document #: 38-07531 Rev. ** Page 9 of 9 |
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